The semiconductor industry is rapidly transitioning from planar field effect transistors to fin type field effect transistors (finFETs), partially due to their density advantage such that the device's effective current-carrying width typically exceeds that of its footprint on the wafer. Inherent to FinFET device design is discretization of this effective width to multiples of twice the fin height (plus the fin thickness, in the case of a tri-gate). The constraint of discretized effective widths means that designers have more constraints in tuning device widths for optimal designs. For example, SRAM cell noise margin optimization frequently requires fine tuning of device width ratios. Various techniques have been attempted for modifying the effective device width of finFET devices. These include changing the physical fin height, and control of epitaxial growth. However, each of these approaches has disadvantages, such as increased fabrication complexity. It is therefore desirable to have improvements in finFET structures and methods of fabrication to address the aforementioned design constraints while avoiding the disadvantages of current techniques.